Verification Engineer Job

VERIFICATION ENGINEER needed for a CONTRACT opportunity with Yoh's client located in Mesa, AZ.

TOP SKILLS YOU SHOULD POSSESS:

- Verification Methodologies
- VHDL
- Verilog

WHAT YOU'LL BE DOING:

- Verification Engineer will define overall verification strategies, methodologies, and simulation environment.
- Verification Engineer will follow common verification methodology for a complex mixed signal communications integrated circuit.
- Verification Engineer will construct Verification Plan from Design Specification, Test Bench Implementation and Bring up
- Verification Engineer will conduct Design Reviews as needed and engage with the team, follow coding guidelines, follow Common Verification Methodology implementing/developing in environments.
- Verification Engineer will Create, track, and close defects using bug tracking tools

WHAT YOU NEED TO BRING TO THE TABLE:

- BS or MS in EE, CS, or related subject area
- Expert level experience with Test Bench set up.
- Experience with Verilog and VHDL
- UVM/OVM experience
- Expert in debugging complex mixed domain issues

BONUS POINTS! OTHERWISE KNOWN AS PREFERRED QUALIFICATIONS:

- Strong Embedded design experience is preferred
- System Verilog Experience is preferred
- Knowledge of cellular telephony and ability to understand analog schematics

WHAT'S IN IT FOR YOU?

- Opportunity to work with teams and equipment at a cutting edge, global innovator

IF THIS SOUNDS LIKE YOU, APPLY NOW!

RECRUITER: Aleks Basalilov

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer, M/F/D/V. Contact us if you are an individual with a disability and require accommodation in the application process.

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