Vakante Jobangebote finden Sie unter Projekte.
Projektbeschreibung
PROJECT START: 1.9.2012
PROJECT DURATION: 9 months
LOCATION: Braunschweig
REQUIRED SKILLS:
- Experienced System Verilog/VHDL verification engineer (used to work with Unix OS, perls scripts, TCL/TK and similar)
- Good OVM understanding and experience in writing and using OVM based testbenches
- Good System Verilog for Verification skills
- Experienced RTL simulator user (DE)/support (DA) (e.g. VCS/Modelsim/ Questa or similar)
- Wave trace debug skills (FSDB)
- If possible: Mentor MBIST / EDT verification skills
If you are interested in this vacancy, we would be pleased to receive your CV together with your availability and financial expectations.
Projektdetails
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Einsatzort:
München, Deutschland
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Projektbeginn:
asap
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Projektdauer:
31.05.13
- Vertragsart:
-
Berufserfahrung:
Keine Angabe
Geforderte Qualifikationen
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Kategorie:
IT Entwicklung, Ingenieurwesen/Technik
Harveynash
