RTL Design and Validation Engineer

For this contract position with the leading computer components company, the RTL DESIGN AND VALIDATION ENGINEER will design and development of components for FPGA based in-socket modules for accelerator and prototyping usages.

DAILY RESPONSIBILITIES:

FPGA based device architecture and micro-architecture, designing and developing RTL code, and validation of a prototype system.

REQUIRED QUALIFICATIONS:

- BS or MS with 5+ years of experience in RTL coding for FPGAs
- Intimate familiarity with FPGA and/or ASIC design tools used for RTL development in synthesis, static timing analysis, and placement and routing, and digital simulations
- SystemVerilog+OVM verification methodology, preferably through real project using Verilog, System Verilog and VHDL
- Excellent communication skills, disciplined design approach, and the ability to work smoothly with a team to produce industry leading architecture validation platforms
- Knowledge in Embedded or low-level hardware and/or software development
- Experience in coding with VHDL or Verilog to specify hardware designs and validation test bench
- Experience in simulating VHDL or Verilog code and perform simulation based debug
- Experienced in using test and measurement equipment in the lab to analyze and debug hardware platforms
- Knowledge of CPU micro-architecture and system architectures

NICE TO HAVE:

- Experience in snoop filtering and other QPI related design issues a big plus
- Experience programming in C and/or C++ and assembly language

Estimated length of assignment: 12 months
Number of positions available: 1
Estimated hours per week: 40
% of travel required: 0
Telecommuting: No

Please include a daytime phone number where you can best be reached along with your Resume. Please also include a brief cover letter outlining your experience as related to this job requirement.

CompuCom is an Equal Opportunity Employer. No 3rd party/recruiters please.