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RF Layout/Physical Designer - CMOS .65
Eingestellt von European Recruitment Ltd
Gesuchte Skills: Designer, Design
Projektbeschreibung
We are looking for candidates familiar with the following;
- Cadence IC 6.x
- Calibre Verification on Leafcell and Macro Level, TopLevel is highly welcome
- C65lp and below (c28lp) Technology Knowledge (Well-concepts, TieDown, Substrat Contacts, )
- Layout of RF layout structures considering matching, leakage, IR drop, performance, symmetry
- Verification methodology DRC, LVS and ERC
Key skills: RF, Mixed-signal, mixed signal, analog, layout, physical design, DRC, LVS, ERC, cadence, IC, calibre verification, Macro, top level, CMOS, C65, 0.65, leakage, layout
If this is something that could be of interest to you, then please send me a CV and I will be in contact!
Projektdetails
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Einsatzort:
Berlin, Deutschland
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Projektbeginn:
asap
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Projektdauer:
6 months +
- Vertragsart:
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Berufserfahrung:
Keine Angabe
Geforderte Qualifikationen
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Kategorie:
Medien/Design