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Digital Verification Engineer UWM (m/f)
Eingestellt von Hays aus Mannheim, Universitätsstadt
Gesuchte Skills: Engineer
Projektbeschreibung
340822/6
IHRE AUFGABEN:
-Work on functional verification of mixed signal SoCs
-Develop environment in UVM (Block/SoC level)
-Write Assertions/Coverage in System Verilog
-Code Coverage and Functional Coverage closure of Modules
-UVM Reg implementation
IHRE QUALIFIKATIONEN:
-Desirable - Understanding of NFC protocol
-Worked on functional verification of mixed signal SoCs
-Developed environment in UVM (Block/SoC level)
-Proficient in writing Assertions/Coverage in System Verilog
-Involved in Code Coverage and Functional Coverage closure of Modules
-Worked on Processor based SoCs.
-UVM Reg understanding and implementation
-Understanding vManger based regression flow
-Good in shell scripting
-Hands-on on Cadence based tools (Incisive/vManager)
WEITERE QUALIFIKATIONEN:
Hardware developer
Projektdetails
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Einsatzort:
Styria, Österreich
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Projektbeginn:
asap
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Projektdauer:
3 MM+
- Vertragsart:
-
Berufserfahrung:
Keine Angabe
Geforderte Qualifikationen
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Kategorie:
Ingenieurwesen/Technik