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Digital Layout Engineer
Eingestellt von Consol Partners
Gesuchte Skills: Design, Engineering, Engineer
Projektbeschreibung
Our customer is a leading telecom solutions provider. Through continuous customer-centric innovation, they have established end-to-end advantages in Telecom Network Infrastructure, Application & Software, Professional Services and Devices. With comprehensive strengths in Wireline, wireless and IP technologies, they have gained a leading position in the All-IP convergence age. Its products and solutions have been deployed in over 100 countries and have served 45 of the world's top 50 telecom operators, as well as one third of the world's population.
JOB DESCRIPTION
As part of its transceiver chip developments, they are working on RF Front End and transceiver chips. The successful candidate will execute the full flow from synthesis netlist to a GDSII, including the timing, power and physical verification. He/she will work together with the Front End team to get to a timing clean design and work with the chip integration team to have the final design correctly integrated in a higher level of hierarchy.
The successful candidate needs to be a technical expert in the following areas covering the digital design flow:
- Logic synthesis: knowledge of physical synthesis is a big plus.
- Writing, understanding and adapting SDC based timing constraints
- Clock tree synthesis (CTS): optimizing the clock tree is essential and often requires a mix of clock tree synthesis and (partial) manual instantiation of the clock tree for the most sensitive parts.
- Placement and routing
- Structured & hierarchical layout, manual placement and routing.
- static timing analysis (STA) and closure
- Signal integrity (SI) analysis and closure
- IR drop analysis
- power analysis (static and dynamic)
- DRC and LVS sign-off.
Required Education and Experience:
- Strongly Desired Education and Experience:
- Minimum 8 years experience
- MS in EE, Computer Engineering, or equivalent field
- Experience with digital hardware: RTL design (VHDL, Verilog), logic optimization, RTL compiler, deep sub-micron.
- Experience with (mainly Cadence) Back End tools: Innovus (CTS, CPF, SDC, STA, SI), Redhawk.
- Prior experience with high speed digital designs is a big plus.
- Good communication skills
- Detail oriented and determined
- Team player
Location
Leuven, Belgium
JOB DESCRIPTION
As part of its transceiver chip developments, they are working on RF Front End and transceiver chips. The successful candidate will execute the full flow from synthesis netlist to a GDSII, including the timing, power and physical verification. He/she will work together with the Front End team to get to a timing clean design and work with the chip integration team to have the final design correctly integrated in a higher level of hierarchy.
The successful candidate needs to be a technical expert in the following areas covering the digital design flow:
- Logic synthesis: knowledge of physical synthesis is a big plus.
- Writing, understanding and adapting SDC based timing constraints
- Clock tree synthesis (CTS): optimizing the clock tree is essential and often requires a mix of clock tree synthesis and (partial) manual instantiation of the clock tree for the most sensitive parts.
- Placement and routing
- Structured & hierarchical layout, manual placement and routing.
- static timing analysis (STA) and closure
- Signal integrity (SI) analysis and closure
- IR drop analysis
- power analysis (static and dynamic)
- DRC and LVS sign-off.
Required Education and Experience:
- Strongly Desired Education and Experience:
- Minimum 8 years experience
- MS in EE, Computer Engineering, or equivalent field
- Experience with digital hardware: RTL design (VHDL, Verilog), logic optimization, RTL compiler, deep sub-micron.
- Experience with (mainly Cadence) Back End tools: Innovus (CTS, CPF, SDC, STA, SI), Redhawk.
- Prior experience with high speed digital designs is a big plus.
- Good communication skills
- Detail oriented and determined
- Team player
Location
Leuven, Belgium
Projektdetails
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik