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Verilog/VHDL Design Engineer
Eingestellt von JAM Recruitment
Gesuchte Skills: Engineer, Design
Projektbeschreibung
You'll integrate with the existing software team to program, using VHDL or Verilog, FPGA chips and follow the project through to the testing and simulation stage.
You must be familiar with Altera FPGA chips, with evidence of programming using Verilog or VHDL within a professional environment, ideally with additional experience using System Verilog. You should also be proficient with ModelSim for simulation purposes. Preference will be shown to candidates with previous industry experience relating to data capture and DMA projects.
For more information on this contract please email your CV or call Jon Armstrong.
Job Title: Verilog/VHDL Design Engineer
Rate: £25 - £35 p/h
Location: Somerset
Duration: 6 months
Apply to: Jon Armstrong
JAM Recruitment is acting as an employment business with regards to this position.
Projektdetails
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Einsatzort:
Somerset, Vereinigtes Königreich
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Projektbeginn:
asap
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Projektdauer:
6 months
- Vertragsart:
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Berufserfahrung:
Keine Angabe
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik