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Verification Engineer - Systemverilog, OVM, UVM, Test, Debug, Network

Eingestellt von Square One Resources

Gesuchte Skills: Network, Engineer, Ip

Projektbeschreibung

Verification Engineer - SystemVerilog, OVM, UVM, Test, Debug, Network - Ireland

Resources are required for a pre-silicon validation of an IP development currently in execution. Debug issues, update and run test cases/regressions. Experience in networking protocols etc would be an advantage.

There are 4 positions available based in Ireland on 6 month rolling contracts paying market rates.

1. 7+ years of Verification Experience

2. SystemVerilog, OVM, UVM background

3. Experience at the IP/Block level and the SOC level

4. Experience with functional coverage, SVA

5. Experience writing and executing test plans and coverage plans

6. Any experience with lo-power verification methodologies, UPF etc. would be a real plus

This is a 6 month rolling contract based in Ireland paying market rates.

They are looking to interview throughout next week with a start date straight after offer.

Verification Engineer - SystemVerilog, OVM, UVM, Test, Debug, Network - Ireland

Projektdetails

  • Einsatzort:

    Irland

  • Projektbeginn:

    asap

  • Projektdauer:

    6 months +

  • Vertragsart:

    Contract

  • Berufserfahrung:

    Keine Angabe

Geforderte Qualifikationen

Square One Resources