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Verification Engineer (m/f)
Eingestellt von Hays aus Mannheim, Universitätsstadt
Gesuchte Skills: Engineering, Perl, Tcl, Engineer
Projektbeschreibung
240495/6
IHRE AUFGABEN:
-IC develpment, presilicon verification on block and top Level employing UVM methodology
-Plan verification workpackages
-Define and implement verification environment
-Develop block and system-level test cases
-Execute verification and analyse verification results, propose design changes, regression test analysis including time constraint solving
-Prepare test patterns and post silicon validation Support quality and yield engineering activities with pre silicon verification methods
IHRE QUALIFIKATIONEN:
-Good understanding of embedded processor based SoC architecture
-Strong competence in assertion based, coverage driven and formal verification, System Verilog, UVM / OVM
-Experience in C#, Make and proficient in scripting using perl, Tcl
-Experience in definition of verification environments and flows
-English
WEITERE QUALIFIKATIONEN:
Hardware developer
Projektdetails
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Einsatzort:
Styria (Austria), Österreich
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Projektbeginn:
asap
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Projektdauer:
6 MM++
- Vertragsart:
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Berufserfahrung:
Keine Angabe
Geforderte Qualifikationen
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Kategorie:
IT Entwicklung, Ingenieurwesen/Technik