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Senior ASIC Physical Design Engineer - *EU Nationals Only*
Eingestellt von Consol Partners
Gesuchte Skills: Design, Engineer
Projektbeschreibung
-At least 7 years of industry experience in ASIC/SoC Design and IP Integration.
- Defining timing constraints/exceptions, updating timing budgets.
-Synthesis using Synopsys Design Compiler
- Place and Route using IC Compiler: floorplanning, placement, custom clock tree synthesis, routing and block finishing.
- Timing closure (PrimeTime)
- Signoff checks: LEC/ATPG/LVS/DRC/ANT. Power and noise analysis. Place and Route flow enhancements in TCL/Perl.
-Low Power Implementation based on UPF (automatic grid synthesis, level shifters & isolation cells insertion),
- Knowledge of the flow up to 28 nm
- In addition, Synthesis and place and route done via Synopsys LYNX cockpit is a real plus.
- Programming skills
- PERL, Python
- Defining timing constraints/exceptions, updating timing budgets.
-Synthesis using Synopsys Design Compiler
- Place and Route using IC Compiler: floorplanning, placement, custom clock tree synthesis, routing and block finishing.
- Timing closure (PrimeTime)
- Signoff checks: LEC/ATPG/LVS/DRC/ANT. Power and noise analysis. Place and Route flow enhancements in TCL/Perl.
-Low Power Implementation based on UPF (automatic grid synthesis, level shifters & isolation cells insertion),
- Knowledge of the flow up to 28 nm
- In addition, Synthesis and place and route done via Synopsys LYNX cockpit is a real plus.
- Programming skills
- PERL, Python
Projektdetails
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik