RTL Designer

RTL Designer, with extensive experience in Front End (RTL) design & micro-arch is now required to join my client in Ireland

Resources are required for RTL coding and pre-silicon validation of an IP development currently in execution. The CWs will have to code RTL to a micro-architecture specification with the RTL code implemented in SystemVerilog. In addition the CWs will have to code RTL cover points and assertions to support the coverage based validation of the IP. The CWs will have to run RTL through a set of tools/flows (eg Lint, Formal Equivalence, Cross Clock checks etc.) to ensure IP code integrity/quality. The CWs will have to be able to come up to speed very quickly so experience in RTL/uArch design is essential. The CWs should also be able to support the pre-silicon validation team by being able to debug issues, update and run test cases/regressions.

Skills:
extensive xperience in Front End (RTL) design & micro-arch
High speed (400MHz +) experience useful with deep sub-micron experience preferable
Knowledge of SystemVerilog/Verilog is essential
Knowledge of SystemVerilog Assertions (SVA) and Lint would be desirable
Familiarity with working with on-chip interconnects, packet processing pipelines would be an advantage

To apply for this position, candidates must be eligible to live and work in the EU

Connectus Technology Limited is acting as an Employment Agency in relation to this vacancy.