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RTL Design Engineer (FPGA, AIC, SOC, Verilog)

Eingestellt von CDI Anderselite Ltd

Gesuchte Skills: Design, Engineer

Projektbeschreibung

RTL DESIGN ENGINEER (FPGA, AIC, SOC, VERILOG)

RTL Design Engineer with FPGA, ASIC or SoC design experience needed for a 6 months contract in Shannon (Ireland)

THE ROLE

- Implementation of complex design blocks using RTL coding techniques
- Micro-architectural specification of complex design blocks development
- Targeting RTL design blocks to FPGA architectures
- Working closely with other teams

THE SKILLS

- FPGA, ASIC or SoC design experience
- RTL level Digital IC design using System Verilog or Verilog
- System Verilog for Verification, OVM/UVM, Perl, Shell Scripting, Altera/Xilinx FPGA Tool Suites
- Experience in CPRI, Ethernet, PCIe, LTE/3G

CDI AndersElite Ltd operates as both an Employment Agency and Employment Business.
Our non-discrimination policy can be viewed on our website at anderselite .com/non-discrimination-policy

Projektdetails

  • Einsatzort:

    Shannon, Irland

  • Projektbeginn:

    asap

  • Projektdauer:

    Keine Angabe

  • Vertragsart:

    Contract

  • Berufserfahrung:

    Keine Angabe

Geforderte Qualifikationen

  • Kategorie:

    Medien/Design, Ingenieurwesen/Technik

  • Skills:

    design, engineer

CDI Anderselite Ltd