RTL Design Engineer Contract 6 - 12 Months

RTL Design Engineer Contract 6 -12 Months Ireland (Shannon). My client a leading global name is in urgent need of a talented and experienced RTL Design engineer to join them on a contract for 6-12 Months.

Your Primary Skills will be System Verilog, RTL, SVA, System Verilog Assertions, On Chip Interconnect, Packet Processing/Networking.

You will be required for RTL coding and pre-silicon validation of an IP development currently in execution. You will have to code RTL to a micro-architecture specification with the RTL code implemented in SystemVerilog. In addition you will have to code RTL cover points and assertions to support the coverage based validation of the IP.

Successful candidates will have Overall 8 years of commercial experience in Front End (RTL) design & micro-arch. Candidates will also have High speed (400MHz +) experience useful with deep sub-micron experience preferable. My client is looking for you to have Knowledge of SystemVerilog/Verilog (essential)

This is unique opportunity to work with a global leading player in their market, if it sounds of interest drop me a line or CV so we can discuss in more detail.