RTL Design Engineer

RTL Design Engineer - FPGA, ASIC - Shannon, Ireland - 6 months - immediate start!

Urgent vacancy for a RTL Design Engineer with in-depth knowledge of FPGA, ASIC and/or SoC design, RTL level Digital IC design using System Verilog and/or Verilog with a proven track record of successful first time delivery of projects. You will also have experience with languages/tools such as System Verilog for Verification, OVM/UVM, Perl, Shell Scripting, Altera/Xilinx FPGA Tool Suites and also have experience in some of the following technologies/protocols: CPRI, Ethernet, PCIe, LTE/3G.

You will be responsible for developing the micro-architectural specification of complex design block(s), logic implementation of complex design block(s) using RTL coding techniques, working with pre-Silicon validation engineers to develop unit and cluster level directed/random tests and environments, targeting (synthesis, place and route and timing closure) RTL design blocks to FPGA architectures, using lab equipment to debug hardware functionality in the lab and interacting closely with other teams such as the Architecture, Software and Post-Silicon Validation.

You will be a self-starter with the ability to assume leadership roles and work well in a diverse team environment and have experience with industry standard development tools and methodologies.