PRE-Silicon Validation Engineer

*Our high-visibility client designs and validates silicon chips with many x86 cores being used in high performance computing architecture.*

Currently this company is seeking a VALIDATION ENGINEER to develop the pre-silicon validation environment and infrastructure for generation of test plan(s) for assigned cluster. This candidate will develop and implement testbench, regression, coverage points, and ensure the coverage goal is met. In addition, s/he will generate and execute tests and identify bugs in the design, and work closely with architecture, micro-architecture and RTL team to resolve the bugs.

Experience and Expertise Level: Mid-Senior Level, minimum of 5 years' experience

REQUIRED SKILLS:

- Knowledge of RTL design and verification language, and ability to work with System Verilog, Specman, OVM/UVM based verification methodology, VCS, Linux, Perl, and C/C++
- Experience in BFM, testbench, checkers/trackers, and test generation and debug
- Experience and understanding of coverage driven verification methods
- Work experience with DDR Memory Controller design and validation a plus

Estimated length of assignment: 12months +
Number of positions available: 1
Estimated hours per week: 40
% of travel required: May travel once a month depending on site location
Telecommuting: No

Please include a daytime phone number where you can best be reached along with your Resume. Please also include a brief cover letter outlining your experience as related to this job requirement.

CompuCom is an Equal Opportunity Employer. No 3rd party/recruiters please.