IC Digital Layout (CMOS) Engineer

CMOS IC DIGITAL LAYOUT ENGINEER

We are looking for a Digital CMOS IC Layout Engineer having the following competences/skills

- security aware floorplanning
- setup CTS (i.a. CPF)
- place & route, timing optimization
- extraction
- security implementation
- timing closure incl. SI
- STA
- formal verification (i.a. CLP)
- voltage drop analysis
- chip finishing
- physical verification

Tools: encounter, QRC, ETS, def_checker, conformal, EPS, PVS

The design is security level 2 design, so level 2 environment is a must (meaning work can only be done on-site)! During tapeout phase (which can last several weeks!) this Back End engineer has to work on site in Austria.

RESPONSIBILITIES

The Digital CMOS IC Layout engineer receives his/her instructions from the design manager and/or from the project leader. He/she decides on technical aspects of the test items and needs to consult the line manager if planning or budget consequences arise from such decisions. The Digital CMOS IC Verification engineer works according to the BU-ID verification way-of-working, but different insights and methods are encouraged.