FPGA Design Engineer

Our client is a very high-visibility computer manufacturing company working on a custom test solution for various industry standard serial bus implementations. Currently this company is looking for a candidate to code RTL for design units, run FPGA synthesis, and place/route and verify timing. S/he will develop and run tests with simulation models.

QUALIFICATIONS

- 5+ years' experience with ASIC Design
- 5+ years' experience with Verification
- 4+ years' experience with RTL development
- 3+ years' experience with RTL development with Verilog
- FPGA synthesis experience
- Experience with Verilog design language
- Experience with simulation environment and test bench development

PREFERRED

- Experience in a lab environment with Logic analyzer/Bus analyzer/Oscope experience
- SDIO2.0 bus design/debug experience
- USB3.0 design/debug experience

Estimated length of assignment: 26 weeks
Number of positions available: 1
Estimated hours per week: 40
% of travel required: 0
Telecommuting: no

Please include a daytime phone number where you can best be reached along with your Resume. Please also include a brief cover letter outlining your experience as related to this job requirement. CompuCom is an Equal Opportunity Employer. No 3rd party/recruiters please.