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Digital Verification Engineer (m/f)
Eingestellt von Hays aus Mannheim, Universitätsstadt
Gesuchte Skills: Design, Engineer, Designer
Projektbeschreibung
336142/6
IHRE AUFGABEN:
-Digital Verification
-Build UVC from scratch
-UVM Methodology
-Debug inside a design
-Help to identify bug
IHRE QUALIFIKATIONEN:
-Experience in UVM System Verilog
-Good understanding of coverage driven random methodology
-Solid coding skill is required
-Experience with building UVC from scratch
-Experience with Cadence verification tool chain, including NCSIM, EPlanner, vManager, IMC
-Eagerness to debug inside a design, helping designer to identify the bug
-Self-driven, good communication skills to work together with designers and concept engineers
-Experience with UVM register model is beneficial
-SVA experience is beneficial
-Experience on coverage mapping using EPlanner is beneficial
-Verification experience with mixed signal design (analog using behavior model) is beneficial
-Gate level verification experience is beneficial
-Experience of Infineon/IMC UVM/OVM environment
-Experience of verifying multi-clock design
WEITERE QUALIFIKATIONEN:
Hardware developer
Projektdetails
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Einsatzort:
Carinthia, Österreich
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Projektbeginn:
asap
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Projektdauer:
6 MM
- Vertragsart:
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Berufserfahrung:
Keine Angabe
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik