Digital Verification Engineer

This position is in the Verification & Validation (V&V) team, which is responsible for performing the Digital V&V simulations of next generation Ethernet Switch.

Responsibilities:
The Digital Verification Engineer is responsible for the setup and execution of IP level UVM tests on moderate to high complexity IP's and/or top level IC's
Work closely together with Architects (System, IC, SW) to understand the overall product concept and to discuss the Verification approach and results.
Analysing defect causes, debugging, root cause analysis of unexpected simulation results
Definition of the V&V simulation infrastructure, including test benches and Verification IP
Coaching/training other Verification engineers
Targeting re-use of V&V components, Infrastructure, tooling and SW.

Required experience:
More than 5 years experience in IP level functional verification using UVM methodology/Specman
Experience in coding with System Verilog, Verilog and VHDL
Experience in programming C, TCL and Perl
Experience with Cadence design environment
Experience with Ethernet domain specific IP's is big plus
Basic knowledge of digital systems
Able to make a clear documentation of designs
Clear and concise communication
Excellent problem solving skills
Team player, self starter
Languages: English, both verbal and in writing.