Digital Dft Designer

Digital DFT Designer/Digital DFT Design Engineer
A leading Semiconductor organisation has a new opportunity for a Digital DFT Designer within their Research and Development department. The successful Digital DFT Designer will be responsible for the architecture and design of all Design For Test/DFT measurements and methods. These will be necessary to enable successful testing and evaluation of the chip. This is an excellent opportunity to join a highly innovative R and D focused organisation within the semiconductor industry.

Responsibilities
You will be responsible for the architecture and RTL design of test circuitry. This will be needed for the testing and evaluation of the chip. You will be working with Digital Designers and Architects to ensure all technical requirements are met. The design flow used is a SOC-flow within the Cadence design environment.
The product range varies from high speed and low voltage communication, image, storage and display circuits to high voltage and high power circuits for lighting and battery management applications.

Expertise
Basic knowledge of digital CMOS circuits and systems
Affinity with analog mixed-signal designs
Working experience of Cadence design environment
At least 5 years` experience in the required field of DFT and Mixed Signal
Experience of using test methods like JTAG, CTAG etc.
Good communication skills