Digital Design Engineer (m/f)

- Defining and implementing design changes (HASTE) for SmartMX products
- Defining and implementing the modifications into verification environment
- Developing SmartMX block and system-level test benches and verification environments using appropriate verification languages
- Executing verification and analyzing verification results in cooperation with block-owner, proposing design changes, regression test analysis including time constraint solving
- Preparing test pattern
- Setup of the lab environment, executing system and block level validation, characterization and evaluation of SmartMX chip functionalities in the lab
- Support of root causing of silicon bugs in cooperation with design team for workaround/fixes
- Driving test bench automation using Labview/script languages, Development/Co-development/improvement of test concepts, test bench maintenance
- Very good Verilog/VHDL knowledge
- Good HASTE knowledge
- Assembler (8051), C/C++, UNIX, Matlab
- HW simulation (NCsim, SimVision)
- Cadence design tools
- TCL, other script languages
- Technical understanding of secure smart cards, especially secure design methodology
- Experience in ASIC/SoC verification methods, tools and flows and should have participated in successful completion of at least one ASIC/SoC project from Specifications to Silicon
- Good understanding of embedded processor based SoC architecture
- Knowledgeable on ASIC verification methodologies and levels - functional, RTL, gate level, timing, etc.,
- Assertion-based coverage driven verification (code & functional coverage), constraint random test generation
- Good understanding about different modeling schemes-TLM, behavior/abstract level, cycle accurate, etc

. - Experience in Make and proficient in scripting using perl, Tcl, etc.
- Experience in semiconductor testing (lab)
- Very good knowledge of lab tools, Labview experience

Weitere Qualifikationen: Hardware developer