Digital CMOS IC Digital Layout Engineer

Job Description Digital CMOS IC Digital Layout Engineer

1.Job definition/Aim of the Job

The Digital CMOS IC Layout engineer executes the layout of digital circuits of high complexity processor based systems

2.Explanatory notes to the organization

The IC Lab located in Eindhoven, The Netherlands, is a unique design house where features for new systems and concepts or prototypes are developed for consumer electronics products and professional applications. IC-Lab specializes in designing complex analog, digital and mixed signal IC`s. We are a customer oriented organization with a strong technology base. This combination creates a dynamic work environment where employees are stimulated to turn innovative ideas into products.

The IC Lab has two analog development groups, and one digital development groups. The way of working covers the complete chain from discussing customer requirements, compiling the specifications, making the design and layout up to the evaluation of the final silicon. The product range varies from high speed and low voltage communication, image, storage and display circuits to high voltage and high power circuits for lighting and battery management applications.

This specific request is about a design of a secure identification design P40 platform in C090 technology.

3.Area of expertise

We are looking for a Digital CMOS IC Layout Engineer having the following competences/skills
-Security aware floorplanning
-Setup CTS (i.a. CPF)
-Place & route, timing optimization
-Extraction
-Security implementation
-Timing closure incl. SI
-STA
-Formal verification (i.a. CLP)
-Voltage drop analysis
-Chip finishing
-Physical verification

Tools: encounter, QRC, ETS, def_checker, conformal, EPS, PVS

The design is security level 2 design, so level 2 environment is a must (meaning work can only be done on-site)! During tapeout phase (which can last several weeks!) this Back End engineer has to work on site in Austria.

4.Responsibilities

The Digital CMOS IC Layout engineer receives his/her instructions from the design manager and/or from the project leader. He/she decides on technical aspects of the test items and needs to consult the line manager if planning or budget consequences arise from such decisions. The Digital CMOS IC Verification engineer works according to the BU-ID verification way-of-working, but different insights and methods are encouraged.