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Design Verification Engineer
Eingestellt von Yoh
Gesuchte Skills: Design, Engineer
Projektbeschreibung
JOB RESPONSIBILITIES:
- Design Verification Engineer will deliver uVM Re-Use ready environments of SoCs including:
- Follow common verification methodology and flow, end-to-end.
- Construct Block level/Sub-system Verification Plan from Design Specification.
- Test Bench Implementation and Bring up.
- RTL Debug and Coverage Closure based on common flow.
- Conduct Design Reviews.
- Work on-site at Irvine office.
- Minimum Weekly Status Sync-up depending on progress.
- Specific work assignments depending on the ability of the Consultant and other area of Sabre verification needs.
- Design Verification Engineer is expected to engage with the team, follow Coding Guidelines, and follow Common Verification Methodology implementing/developing in environments. The completion of this work will include training for the team for the exact changes performed.
Job Qualifications:
- BS or MS in EE, CS, or related subject area.
- Expert level experience with Test Bench set up.
- UVM experience is a must.
- Able to work onsite for at least two (2) months, remote work is possible.
DISCOVER ALL THAT'S POSSIBLE WITH YOH. APPLY NOW.
RECRUITER: Aleks B
Yoh is a professional staffing provider with over 70 years of experience in the short- and long-term staffing services industry.
Yoh, a Day and Zimmermann company, is an Equal Opportunity Employer, M/F/D/V.
J2W: ENG; J2W: INFOTECH
Tax Term: CON_W2J2WBRLA
Ref:
SFSF: ENG
Projektdetails
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Einsatzort:
Irvine, Vereinigte Staaten
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Projektbeginn:
asap
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Projektdauer:
Keine Angabe
- Vertragsart:
-
Berufserfahrung:
Keine Angabe
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik