Design Verification Engineer

HIGH PERFORMANCE ETHERNET NETWORKING

This is a contract opportunity with a group that is responsible for creating several cluster test benches for advanced Ethernet controllers that combine networking, storage, and high performance computing functionality at 10/40Gb speeds. These test benches are implemented using the Specman `e' language with UVM. As part of the pre-silicon Architectural Validation (AV) team you'll help develop test plans from architecture and design specifications, design test benches, write tests, gather and analyze coverage results, plug coverage holes, and debug problems in the design and AV environment. Knowledge of the following is a plus: Ethernet, TCP/IP, any protocols running on top of TCP, digital logic simulation, OVM/UVM/VMM, System Verilog, Specman, C++.

Estimated length of assignment: 6 months
Number of positions available: 1
Estimated hours per week: 40
% of travel required: 0
Telecommuting: Yes

Please include a daytime phone number where you can best be reached along with your Resume. Please also include a brief cover letter outlining your experience as related to this job requirement. CompuCom is an Equal Opportunity Employer. No 3rd party/recruiters please.