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Custom Layout Designer for Advanced node Test chip Development (m/f)
Eingestellt von Hays aus Mannheim, Universitätsstadt
Gesuchte Skills: Design, Designer, Ip
Projektbeschreibung
311479/1
IHRE AUFGABEN:
-Layout of complex memory IP for process development
-Bottom up layout based on custom design schematics
-Schematic driven layout of assigned circuits with the Cadence Virtuoso tool suite
-Completion of the layout using LVS and DRC including colouring and fill
-Handling layout revision caused by post-layout iterations with design as well as technology changes (Booleans, design rules, PDK)
-Preparation and co-presentation at layout reviews
IHRE QUALIFIKATIONEN:
-Familiar with the Cadence Virtuoso tool suite
-Experience with Mentor Calibre LVS and DRC tools
-Know-how regarding advanced node CMOS technologies (equal or less than 40nm)
WEITERE QUALIFIKATIONEN:
Hardware developer
Projektdetails
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Einsatzort:
Saxony, Deutschland
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Projektbeginn:
asap
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Projektdauer:
3 MM++
- Vertragsart:
-
Berufserfahrung:
Keine Angabe
Geforderte Qualifikationen
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Kategorie:
IT Entwicklung, Medien/Design