Component Design Engineer - System Verilog, RTL, ASIC, FPGA

PROJECT DESCRIPTION:
We are porting a PCIe-related design from an ASIC to an FPGA. We will prune features from the design in order to fit it into the FPGA. We will also make minor modifications and re-arrange some blocks, such as configuration registers.

QUALIFICATIONS:
Candidate should have completed 2 full ASIC or FPGA projects, from RTL design through post-silicon validation. Should be able to independently design and validate a simple logic block, given a high level description of the design requirements. This is approximately 4 years of experience.

Daily Responsibilities:
Major tasks include: 
* Analyzing an existing configuration register block to determine the optimal grouping of registers so that this block can be split into several smaller blocks, to reduce cross-chip routing
* Instantiating a controller for the register bus in each of the new register blocks
* Testing the design
* Solving timing issues related to the assigned blocks

Necessary Skills (Must Have):
* RTL design using System Verilog and Verilog
* RTL validation using System Verilog and Verilog
* Using RTL coding style conducive for synthesis and timing closure
* Analyzing and fixing timing paths

Additional Skills Desired (Nice to Have):
* FPGA synthesis
* Perl or Tcl Scripting

Please include a daytime phone number where you can best be reached along with your Resume. Please also include a brief cover letter outlining your experience as related to this job requirement. CompuCom is an Equal Opportunity Employer. No 3rd party/recruiters please.