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ASIC Verification Engineer
Eingestellt von Aardvark Consulting
Gesuchte Skills: Engineer, Design, Designer
Projektbeschreibung
Job Title: ASIC Verification Engineer
Contract Length: Six (6) months with possibility for further extension.
Start date: 2014-06-01.
End date: 2014-11-30.
Location: Lund, Sweden
Job description
The job involves block verification within company's digital ASIC projects.
The goal of the block verification is to verify that the functional requirements of our blocks are fulfilled before tape-out of the ASIC.
The work includes:
* Verification planning.
* Verification specification.
* Verification environment (creation/adaptation/maintenance).
* Test case creation.
* Usage of uVC's.
* Development of uVC's (if needed).
* Usage of reference models (if needed).
* Constrained random testing.
* Creation of Coverage Matrix.
* Writing Verification Reports.
* Etc.
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used. A successful candidate is an experienced verification engineer with 5 or more years of verification experience. Specman or System Verilog competence as well as good understanding and knowledge about HW designs are also key factors. Both written and spoken English skills are required. Personal profile should also include a positive attitude, a desire to assist fellow engineers, structured way of working, care with details and a natural talent in communicating with others. You enjoy working both independently and in a small team and you are focused on reaching result on time. As a person you must be thorough and able to work with many different people. The work will be carried out in close cooperation with the block designer.
Required competence
* Experienced in using the Specman tools or System Verilog tools.
* Excellent programming skills (E).
* Good programming skills (C).
* Experience of SW design for an Embedded environment.
* Knowledge of hardware design (VHDL/Verilog).
* Knowledge of verification methodology.
* Education level: Master of Science or similar.
Desired competence
* Experience in HW verification using eg OVM/UVM.
* Experience in system level verification.
* Experience in Formal Verification.
* Experienced in WCDMA, GSM and/or LTE systems.
Contract Length: Six (6) months with possibility for further extension.
Start date: 2014-06-01.
End date: 2014-11-30.
Location: Lund, Sweden
Job description
The job involves block verification within company's digital ASIC projects.
The goal of the block verification is to verify that the functional requirements of our blocks are fulfilled before tape-out of the ASIC.
The work includes:
* Verification planning.
* Verification specification.
* Verification environment (creation/adaptation/maintenance).
* Test case creation.
* Usage of uVC's.
* Development of uVC's (if needed).
* Usage of reference models (if needed).
* Constrained random testing.
* Creation of Coverage Matrix.
* Writing Verification Reports.
* Etc.
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used. A successful candidate is an experienced verification engineer with 5 or more years of verification experience. Specman or System Verilog competence as well as good understanding and knowledge about HW designs are also key factors. Both written and spoken English skills are required. Personal profile should also include a positive attitude, a desire to assist fellow engineers, structured way of working, care with details and a natural talent in communicating with others. You enjoy working both independently and in a small team and you are focused on reaching result on time. As a person you must be thorough and able to work with many different people. The work will be carried out in close cooperation with the block designer.
Required competence
* Experienced in using the Specman tools or System Verilog tools.
* Excellent programming skills (E).
* Good programming skills (C).
* Experience of SW design for an Embedded environment.
* Knowledge of hardware design (VHDL/Verilog).
* Knowledge of verification methodology.
* Education level: Master of Science or similar.
Desired competence
* Experience in HW verification using eg OVM/UVM.
* Experience in system level verification.
* Experience in Formal Verification.
* Experienced in WCDMA, GSM and/or LTE systems.
Projektdetails
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik