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ASIC Verification Engineer
Eingestellt von Tangent International
Gesuchte Skills: Engineer, Design, Designer
Projektbeschreibung
We are looking for a skilled ASIC Verification Engineer to join a leading mobile/technology brand at their site in Lund, Sweden.The job involves block verification within our customers digital ASIC projects, this is to verify that the functional requirements of our blocks are fulfilled before tape-out of the ASIC. Specman competence, knowledge about HW designs are also key factor and experience in System Verilog.Both written and spoken English skills are required. Positive attitude, team work, structured way of working, attention to detail. Working both independently, or in a team, result driven. The work will be carried out in close cooperation with the block designer.
About the Client Company
Top mobile/technology organisation
Duties & Responsibilities
-Verification planning and specification
-Verification environment (creation/adaptation/maintenance).
-Test case creation -Usage of uVC´s, development of uVC´s (if needed)
-Usage of reference models (if needed)
-Constrained random testing
-Creation of Coverage Matrix
-Writing Verification Reports
-Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.
Key Benefits
Working in a hi-tech environment, with latest technologies
Candidate Skills & Requirements
Atleast 5 or more years of verification experience.
Required competence Experienced in Specman tools Excellent programming skills (E)
Good programming skills (C)
Experience of SW design for an Embedded environment
Knowledge of hardware design (VHDL/Verilog)
Knowledge of verification methodology
Education level:
Master of Science or similar
Desired competence
Experience in HW verification using eg OVM/UVM
Experience in system level verification
Experience in System Verilog.
Experienced in WCDMA, GSM and/or LTE systems
About the Client Company
Top mobile/technology organisation
Duties & Responsibilities
-Verification planning and specification
-Verification environment (creation/adaptation/maintenance).
-Test case creation -Usage of uVC´s, development of uVC´s (if needed)
-Usage of reference models (if needed)
-Constrained random testing
-Creation of Coverage Matrix
-Writing Verification Reports
-Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.
Key Benefits
Working in a hi-tech environment, with latest technologies
Candidate Skills & Requirements
Atleast 5 or more years of verification experience.
Required competence Experienced in Specman tools Excellent programming skills (E)
Good programming skills (C)
Experience of SW design for an Embedded environment
Knowledge of hardware design (VHDL/Verilog)
Knowledge of verification methodology
Education level:
Master of Science or similar
Desired competence
Experience in HW verification using eg OVM/UVM
Experience in system level verification
Experience in System Verilog.
Experienced in WCDMA, GSM and/or LTE systems
Projektdetails
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik