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ASIC Verification
Eingestellt von PROTEUS EUROPE
Gesuchte Skills: Engineer, Design
Projektbeschreibung
Proteus Europe operating as an employment business, is currently seeking an ASIC Verification engineer for a client in Sweden.
The job involves block verification within digital ASIC projects.
The goal of the block verification is to verify that the functional requirements of our blocks are fulfilled before tape-out of the ASIC.
The work includes:
- Verification planning
- Verification specification
- Verification environment (creation/adaptation/maintenance).
- Test case creation Usage of uVC´s
- Development of uVC´s (if needed)
- Usage of reference models (if needed)
- Constrained random testing Creation of Coverage Matrix Writing Verification Reports Etc.
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.
A successful candidate is an experienced verification engineer with 5 or more years of verification experience. Specman competence as well as good understanding and knowledge about HW designs are also key factors. Knowledge and experience in System Verilog is also appreciated.
Required competence
- Experienced in using the Specman tools
- Excellent programming skills (E)
- Good programming skills (C)
- Experience of SW design for an Embedded environment
- Knowledge of hardware design (VHDL/Verilog)
- Knowledge of verification methodology
- Education level: Master of Science or similar
Desired competence
- Experience in HW verification using eg OVM/UVM
- Experience in system level verification
- Experience in System Verilog
- Experienced in WCDMA, GSM and/or LTE systems
The job involves block verification within digital ASIC projects.
The goal of the block verification is to verify that the functional requirements of our blocks are fulfilled before tape-out of the ASIC.
The work includes:
- Verification planning
- Verification specification
- Verification environment (creation/adaptation/maintenance).
- Test case creation Usage of uVC´s
- Development of uVC´s (if needed)
- Usage of reference models (if needed)
- Constrained random testing Creation of Coverage Matrix Writing Verification Reports Etc.
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.
A successful candidate is an experienced verification engineer with 5 or more years of verification experience. Specman competence as well as good understanding and knowledge about HW designs are also key factors. Knowledge and experience in System Verilog is also appreciated.
Required competence
- Experienced in using the Specman tools
- Excellent programming skills (E)
- Good programming skills (C)
- Experience of SW design for an Embedded environment
- Knowledge of hardware design (VHDL/Verilog)
- Knowledge of verification methodology
- Education level: Master of Science or similar
Desired competence
- Experience in HW verification using eg OVM/UVM
- Experience in system level verification
- Experience in System Verilog
- Experienced in WCDMA, GSM and/or LTE systems
Projektdetails
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik