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ASIC, FPGA Test Engineer (Design for Testability) - DFT, low Power aud
Eingestellt von John Whelan Associates Ltd
Gesuchte Skills: Design, Engineer
Projektbeschreibung
Are you a senior engineer who has worked with Philips and/or NXP design workflows?
In addition do you have experience of designing and developing DFT (design for testability) based test programs for ASIC/FPGA?
We are urgently searching for senior test specialists with experience of DFT to develop test programs and interfaces to test automation systems for low power ASIC design and validation projects concerning audio processing.
Our customer has requested a senior engineer with over 10 years industrial experience and in this context we anticipate a pay rate of circa 62 per hour, depending on relevant skills match.
Ideally candidates will have some Dutch/Flemish language skills, but this may not be a stopping point if your experience of DFT is strong.
Further information regarding skills and abilities available, please send your CV and contact telephone number.
In addition do you have experience of designing and developing DFT (design for testability) based test programs for ASIC/FPGA?
We are urgently searching for senior test specialists with experience of DFT to develop test programs and interfaces to test automation systems for low power ASIC design and validation projects concerning audio processing.
Our customer has requested a senior engineer with over 10 years industrial experience and in this context we anticipate a pay rate of circa 62 per hour, depending on relevant skills match.
Ideally candidates will have some Dutch/Flemish language skills, but this may not be a stopping point if your experience of DFT is strong.
Further information regarding skills and abilities available, please send your CV and contact telephone number.
Projektdetails
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik