Vakante Jobangebote finden Sie unter Projekte.
ASIC Design Verification Engineer Job
Eingestellt von Yoh
Gesuchte Skills: Design, Engineer
Projektbeschreibung
THE BIG PICTURE - TOP SKILLS YOU SHOULD POSSESS:
- UVM
- System Verilog
- Scripting in any language
WHAT YOU'LL BE DOING:
- Leading verification of complex design blocks
- Defining and implementing verification infrastructure using System Verilog and UVM
- Developing verification plans including coverage metrics
- Implementing test benches, direct and constrained random tests
- Working independently to debug RTL and communicate results with the design team
- Coverage closure to achieve verification goals.
- Documentation.
WHAT YOU NEED TO BRING TO THE TABLE:
- Extensive knowledge of design verification of complex designs using advanced verification methods.
- Expert level knowledge of System Verilog.
- Expertise in developing SystemVerilog/UVM based DV environments, test plans, testbenches, assertions, coverage
- Knowledge of Scripting languages such as TCL, Perl or Python
- Strong communications skills
- Ability to work with minimal direction in a fast paced team environment
BONUS POINTS!
- Knowledge of high speed interfaces such as PCIe, Ethernet, DDR3/4 is highly desirable
GET HIRED. APPLY NOW!
RECRUITER: Nikki Sloan
Yoh, a DayTHIS ADDRESS IS EXCLUSIVELY FOR INDIVIDUALS WITH DISABILITIES REQUESTING APPLICATION ASSISTANCE.
J2W: INFOTECH; J2W: ENG
Tax Term: CON_W2J2WBRSILIV
Ref:
Branch: IT & Telecom
Projektdetails
-
Einsatzort:
Mountain View, Vereinigte Staaten
-
Projektbeginn:
asap
-
Projektdauer:
Keine Angabe
- Vertragsart:
-
Berufserfahrung:
Keine Angabe
Geforderte Qualifikationen
-
Kategorie:
Medien/Design, Ingenieurwesen/Technik