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ASIC Design Engineer - Cadence, VHDL, Verilog
Eingestellt von John Whelan Associates Ltd
Gesuchte Skills: Design, Engineer
Projektbeschreibung
We are urgently searching for an ASIC design and verification engineer to work on implementing and verifying the digital MAC design part of a wireless communication system ASIC.
You will need experience of VHDL, Cadence digital simulation tools and System Verilog.
This is a 12 month project onsite with our client, a leading vendor within the semiconductor sector. Very good rates offered, please apply for further information.
You will need experience of VHDL, Cadence digital simulation tools and System Verilog.
This is a 12 month project onsite with our client, a leading vendor within the semiconductor sector. Very good rates offered, please apply for further information.
Projektdetails
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik