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AS IC Analog Layouter
Eingestellt von Consol Partners
Gesuchte Skills: Engineer, Designer
Projektbeschreibung
Belgian & French Research Centers
ConSol Partners client, a large & leading Telecoms provider are searching for an IC Layouter to work on developing the next generation of RF transceivers, front-ends and peripheral circuits, supporting 2G, 3G and 4G (LTE) protocols.
In their advanced R&D team, in which you will also be working they are also pioneering the next generation 5G cellular chipsets.
You can decide to work in either Leuven, Belgium or Sophia Antipolis (Nice), France. You will be required full time on site 5 days per week.Job Description
We are offering a senior layout engineer position enabling you to join the creation of the next generation mobile phone chips.
The Analog & RF IC Layout Engineer will be part of an experienced layout team. In close cooperation with hher/is colleagues s/he will be in charge of the layout of high speed analog and RF circuits and s/he will take up a leading role in the floorplanning and optimization of the system on chip.
S/He is an expert user of Cadence and Mentor tool suites on nanometer RF CMOS and/or RF SOI technology.
The successful candidate will work closely with the RF designers. He/she will take into account the constraints from the designer and will go through iterations with the designer to further optimize the layout from a performance and area perspective.
RF circuit layout experience in the sub 10-Ghz range is mandatory.
The layout engineer should have a good understanding of the different circuit topologies and their constraints for the layout. implementation. Good understanding of the layout rules enables to optimize the implementation.
The senior layout engineer is also capable to perform extraction of parasitics and make the interpretation of these results in view of further optimization.Required Education and Experience:
- Industry Degree qualified (BS or MS EE degree)
- Ample experience with the Cadence OA VirtuosoXL
- Experience with RFIC layout (GHz range) in CMOS technology
- Finfet experience is a major plus.
- Automation for layout is a plus.
- Good communication skills & team-player.
- Process oriented, ability to structure the RF layout process
- Continuous strive for improvement in circuits and process.
- Detail oriented and determined
LOCATION
Leuven, Belgium or Sophia Antipolis, France
ConSol Partners client, a large & leading Telecoms provider are searching for an IC Layouter to work on developing the next generation of RF transceivers, front-ends and peripheral circuits, supporting 2G, 3G and 4G (LTE) protocols.
In their advanced R&D team, in which you will also be working they are also pioneering the next generation 5G cellular chipsets.
You can decide to work in either Leuven, Belgium or Sophia Antipolis (Nice), France. You will be required full time on site 5 days per week.Job Description
We are offering a senior layout engineer position enabling you to join the creation of the next generation mobile phone chips.
The Analog & RF IC Layout Engineer will be part of an experienced layout team. In close cooperation with hher/is colleagues s/he will be in charge of the layout of high speed analog and RF circuits and s/he will take up a leading role in the floorplanning and optimization of the system on chip.
S/He is an expert user of Cadence and Mentor tool suites on nanometer RF CMOS and/or RF SOI technology.
The successful candidate will work closely with the RF designers. He/she will take into account the constraints from the designer and will go through iterations with the designer to further optimize the layout from a performance and area perspective.
RF circuit layout experience in the sub 10-Ghz range is mandatory.
The layout engineer should have a good understanding of the different circuit topologies and their constraints for the layout. implementation. Good understanding of the layout rules enables to optimize the implementation.
The senior layout engineer is also capable to perform extraction of parasitics and make the interpretation of these results in view of further optimization.Required Education and Experience:
- Industry Degree qualified (BS or MS EE degree)
- Ample experience with the Cadence OA VirtuosoXL
- Experience with RFIC layout (GHz range) in CMOS technology
- Finfet experience is a major plus.
- Automation for layout is a plus.
- Good communication skills & team-player.
- Process oriented, ability to structure the RF layout process
- Continuous strive for improvement in circuits and process.
- Detail oriented and determined
LOCATION
Leuven, Belgium or Sophia Antipolis, France
Projektdetails
Geforderte Qualifikationen
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Kategorie:
Medien/Design, Ingenieurwesen/Technik