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Analog Layout Engineer - Temporary 2-year Contract (m/f)

Eingestellt von Intel - Germany

Gesuchte Skills: Engineering, Design, Engineer, Designer

Projektbeschreibung

Job Description - Analog Layout Engineer - Temporary 2 year contract (m/f) (783039) Job Description Analog Layout Engineer - Temporary 2 year contract (m/f) - 783039 Description Electro Static Discharge (ESD) is a real challenge for ultra low scale CMOS designs. We are developing ESD protection elements for all IO's and analog RF IP blocks as well as HV designs. This reaches from standard CMOS IOs over High Speed interfaces to Power management solutions. This elements are provided within an ESD Library to our product design teams. We are looking for you to do the Physical design of the ESD Library and the ESD test kits in close interaction with our ESD development Engineers and application engineers. You will join a brilliant team in ESD and Latch up protection and be its face towards the RF product designs. A state of-the art equipped laboratory and well established tools for ESD development and design verification are providing the right working environment. Responsibilities include, but are not limited to: - Layout of ESD Library - Verification, documentation, release on data pool and distribution of ESD Library - Layout of ESD cell test kit - Enable ESD cell Library for latest ESD verification and design tools e.g. power planner, ESD runsets... - Review of ESD cell implementation in IO Libraries and full custom designs - Consulting of designer on ESD optimized Layout and power routing Qualifications You should provide following qualifications: Bachelor or comparable education. 5+ Years of experience in physical design / analog layout You should have deep know how within the following Tools: Virtuoso XL (Cadence), Calibre (Mentor Graphics), Assura Job Category: Engineering Primary Location: Germany Germany, Munich Full/Part Time: Full Time Job Type: Intel Contract Employee Regular/Temporary: Temporary Posting Date: Dec 7, 2015 Apply Before: Ongoing Business Group The Platform Engineering Group (PEG) is responsible for the design, development, and production of system on-a chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering. Posting Statement: N/A If you are interested in this job, please apply directly by sending your application to with reference to DICE and the job number.

Projektdetails

  • Vertragsart:

    Contract

  • Berufserfahrung:

    Keine Angabe

Geforderte Qualifikationen

Intel - Germany