Hardware Engineer

As part of transceiver development, my client develops high speed (1-10GHz) low power digital circuits in advanced CMOS nodes. The successful candidate will assume full responsibility of layout generation for these circuits. He/she will try to meet the tough timing requirements by careful design and control of the layout generation, making use of structured layout and controlled placement techniques and (partly) manual control of the routing wherever needed. They need to be able to evaluate where the (timing) problems arise and fix them, or if that is not possible, interact pro-actively with the RTL-to-gates designer to fix the issues at that level.

The successful candidate needs to be a technical expert in the areas of Cadence encounter based layout generation: clock tree synthesis (CTS), multi-power routing (CPF based, IR drop analysis), static timing analysis (STA) and closure, signal integrity (SI) analysis and closure, structured & hierarchical layout (ILM flow), power analysis (static and dynamic), DRC and LVS sign-off, in advanced CMOS nodes and for very high-speed designs.

A good knowledge of and experience in RTL design and logic optimization is a big plus.

Minimum 10 years experience
MS in EE, Computer Engineering, or equivalent field
Silicon validation experience is important
Experience with digital hardware: RTL design (VHDL, Verilog), logic optimization, RTL compiler, deep sub-micron.
Experience with Back End Cadence tools: Encounter (CTS, CPF, STA, SI, ILM, ).
Good communication skills
Detail oriented and determined
Team player